Cwazibeh

This practical provides an introduction to some of the computer-based tools provided by Altera Corporation for designing and implementing digital circuits on their programmable logic devices. A single afternoon has been set aside for the laboratory and each group will be supplied with a PC running the Altera MAX plus II software, a device programmer, and a test bench for implementing the designs.

ATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein

This practical provides an opportunity to design sequential circuits. A single afternoon has been allocated for this practical, which consists of two major tasks

Asynchronous sequential systems have no clock; internal states change when there is a change in the input variables. • Memory is achieved by the unclocked latches, delay elements, or Inherent delay in circuits. • Asynchronous sequential systems are used where a fast response to input changes, without having to wait for a clock transition, is necessary. • Asynchronous sequential systems are also used where the introduction of extra frequency components related to the clock must be avoided. ...

nvestigate the transition table of the figure below and determine the race conditions. State whether they are critical or noncritical

urpose: To reduce the number of states in a FSM definition without altering the input/output relationship. • Motivation: lower cost- number of states is closely related to the complexity of the resulting circuit; – fewer flip-flops in implementations. – more don’t cares in next state logic. – fewer gates in next state logic. – Simpler to design with extra states then reduce later. • Several Methods of state Reduction

vestigate the transition table of the figure below and determine the race conditions. State whether they are critical or noncritical. 2

vestigate the transition table of the figure below and determine the race conditions. State whether they are critical or noncritical. 2

Hardware description languages (HDLs) are used to design chips. We write an HDL program to design a chip just like we draw a schematic to design a chip. • Why an HDL program, why not schematics ? –

btain a primitive flow table from the given specification. • Reduce the flow table by merging rows in the primitive flow table. (STATE REDUCTION) • Assign binary states variables to each row of the reduced flow table to obtain the transition table. (STATE ASSIGNMENT-RACES) • Assign output values to the dashes associated with the unstable states to obtain the output maps. • Simplify the boolean functions of the excitation and output variables (HARZARDS) and draw the logic diagram.